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FEATURES Low Supply Current: 4 A/Amplifier max Single-Supply Operation: 2.7 V to 12 V Wide Input Voltage Range Rail-to-Rail Output Swing Low Offset Voltage: 1.5 mV No Phase Reversal APPLICATIONS Comparator Battery Powered Instrumentation Safety Monitoring Remote Sensors Low Voltage Strain Gage Amplifiers
Ultralow Power, Rail-to-Rail Output Operational Amplifiers OP181/OP281/OP481
PIN CONFIGURATIONS 8-Lead SO (S Suffix)
NULL -IN A +IN A V- 1 8 NC V+ OUT A NULL
8-Lead Epoxy DIP (P Suffix)
NULL 1 -IN A 2 +IN A 3 V- 4 8 NC
OP181
4 5
OP181
7 V+ 6 OUT A 5 NULL
NC = NO CONNECT
NC = NO CONNECT
8-Lead SO (S Suffix)
OUT A -IN A +IN A V- 1 8 V+ OUT B -IN B +IN B
8-Lead Epoxy DIP (P Suffix)
OUT A 1 -IN A 2 +IN A 3 V- 4
OP281
8 V+ 7 OUT B 6 -IN B 5 +IN B
OP281
4 5
GENERAL DESCRIPTION
The OP181, OP281 and OP481 are single, dual and quad ultralow power, single-supply amplifiers featuring rail-to-rail outputs. All operate from supplies as low as 2.0 V and are specified at +3 V and +5 V single supply as well as 5 V dual supplies. Fabricated on Analog Devices' CBCMOS process, the OP181 family features a precision bipolar input and an output that swings to within millivolts of the supplies and continues to sink or source current all the way to the supplies. Applications for these amplifiers include safety monitoring, portable equipment, battery and power supply control, and signal conditioning and interface for transducers in very low power systems. The output's ability to swing rail-to-rail and not increase supply current, when the output is driven to a supply voltage, enables the OP181 family to be used as comparators in very low power systems. This is enhanced by their fast saturation recovery time. Propagation delays are 250 s. The OP181/OP281/OP481 are specified over the extended industrial (-40C to +85C) temperature range. The OP181, single, and OP281, dual, amplifiers are available in 8-pin plastic DIPs and SO surface mount packages. The OP281 is also available in 8-lead TSSOP. The OP481 quad is available in 14pin DIPs, narrow 14-pin SO and TSSOP packages.
8-Lead TSSOP (RU Suffix)
1 4 8 5
OP281
14-Lead Epoxy DIP (P Suffix)
14-Lead Narrow-Body SO (S Suffix)
1 14
OUT A 1 -IN A 2 +IN A 3 V+ 4 +IN B 5 -IN B 6 OUT B 7
14 OUT D 13 -IN D 12 +IN D
OP481
OP481
11 V- 10 +IN C 9 -IN C 8 OUT C 7 8
14-Lead TSSOP (RU Suffix)
1 14
OP481
NOTE: PIN ORIENTATION IS EQUIVALENT FOR EACH PACKAGE VARIATION 7 8
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 (c) Analog Devices, Inc., 1996
OP181/OP281/OP481-SPECIFICATIONS
ELECTRICAL SPECIFICATIONS (@ V = +3.0 V, V
S CM
= 1.5 V, TA = +25 C unless otherwise noted)
Min Typ Max 1.5 2.5 10 7 2 Units mV mV nA nA V dB V/mV V/mV V/C pA/C pA/C
Parameter INPUT CHARACTERISTICS Offset Voltage Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Offset Voltage Drift Bias Current Drift Offset Current Drift OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Short Circuit Limit POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Turn On Time Turn On Time Saturation Recovery Time Gain Bandwidth Product Phase Margin NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density
NOTES 1 VOS is tested under no load condition. Specifications subject to change without notice.
Symbol VOS IB IOS CMRR AVO VOS/T IB/T IOS/T VOH VOL ISC PSRR ISY
Conditions Note 1 -40C TA +85C -40C TA +85C -40C TA +85C
3 0.1 0
VCM = 0 V to 2.0 V, -40C TA +85C RL = 1 M, VO = 0.3 V to 2.7 V -40C TA +85C
65 5 2
95 13 10 20 2
RL = 100 k to GND, -40C TA +85C RL = 100 k to V+, -40C TA +85C
2.925
2.96 25 1.1 75
V mV mA
VS = 2.7 V to 12 V -40C TA +85C VO = 0 V -40C TA +85C RL = 100 k, CL = 50 pF AV = 1, VO = 1 AV = 20, VO = 1
76
95 3
4 5
dB A A V/ms s s s kHz Degrees V p-p nV/Hz pA/Hz
SR
GBP o en p-p en in 0.1 Hz to 10 Hz f = 1 kHz
25 40 50 65 95 70 10 75 <1
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OP181/OP281/OP481 ELECTRICAL SPECIFICATIONS (@ V = +5.0 V, V
S CM
= 2.5 V, TA = +25 C unless otherwise noted1)
Min Typ 0.1 3 0.1 0 Max 1.5 2.5 10 7 4 Units mV mV nA nA V dB V/mV V/mV V/C pA/C pA/C
Parameter INPUT CHARACTERISTICS Offset Voltage Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Offset Voltage Drift Bias Current Drift Offset Current Drift OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Short Circuit Limit POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Saturation Recovery Time Gain Bandwidth Product Phase Margin NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density
NOTES 1 VOS is tested under a no load condition. Specifications subject to change without notice.
Symbol VOS IB IOS CMRR AVO VOS/T IB/T IOS/T VOH VOL ISC PSRR ISY
Conditions Note 1 -40C TA +85C -40C TA +85C -40C TA +85C VCM = 0 V to 4.0 V, -40C TA +85C RL = 1 M , VO = 0.5 V to 4.5 V -40C TA +85C -40C to +85C
65 5 2
90 15 10 20 2
RL = 100 k to GND, -40C TA +85C RL = 100 k to V+, -40C TA +85C
4.925
4.96 25 3.5 75
V mV mA
VS = 2.7 V to 12 V, -40C TA +85C VO = 0 V -40C TA +85C RL = 100 k, CL = 50 pF
76
95 3.2
4 5
dB A A V/ms s kHz Degrees V p-p nV/Hz pA/Hz
SR GBP o en p-p en in
27 120 100 74 10 75 <1
0.1 Hz to 10 Hz f = 1 kHz
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OP181/OP281/OP481-SPECIFICATIONS
ELECTRICAL SPECIFICATIONS (@ V = 5 V, T = +25 C unless otherwise noted)
S A
Parameter INPUT CHARACTERISTICS Offset Voltage Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Large Signal Voltage Gain Offset Voltage Drift Bias Current Drift Offset Current Drift OUTPUT CHARACTERISTICS Output Voltage Swing Short Circuit Limit POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product Phase Margin NOISE PERFORMANCE Voltage Noise Voltage Noise Density Voltage Noise Density Current Noise Density
NOTES 1 VOS is tested under no load condition. Specifications subject to change without notice.
Symbol VOS IB IOS CMRR AVO VOS/T IB/T IOS/T VO ISC PSRR ISY
Conditions Note 1 -40C TA +85C -40C TA +85C -40C TA +85C
Min
Typ 0.1 3 0.1
Max 1.5 2.5 10 7 +4
Units mV mV nA nA V dB V/mV V/mV V/C pA/C pA/C
-5 VCM = -5.0 V to +4.0 V, -40C TA +85C RL = 1 M, VO = 4.0 V, -40C TA +85C -40C to +85C 65 5 2 95 13 10 20 2
RL = 100 k to GND, -40C TA +85C
4.925
4.98 12
V mA
VS = 1.35 V to 6 V, -40C TA +85C VO = 0 V -40C TA +85C RL = 100 k, CL = 50 pF
76
95 3.3
5 6
dB A A V/ms kHz Degrees V p-p nV/Hz nV/Hz pA/Hz
SR GBP o en p-p en en in
28 105 75 10 85 75 <1
0.1 Hz to 10 Hz f = 1 kHz f = 10 kHz
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OP181/OP281/OP481
ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +16 V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . Gnd to VS + 10 V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . 3.5 V Output Short-Circuit Duration to Gnd . . . . . . . . . . Indefinite Storage Temperature Range P, S, RU Package . . . . . . . . . . . . . . . . . . . -65C to +150C Operating Temperature Range OP181/OP281/OP481G . . . . . . . . . . . . . . . -40C to +85C Junction Temperature Range P, S, RU Package . . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300C Package Type 8-Pin Plastic DIP (P) 8-Pin SOIC (S) 8-Pin TSSOP (RU) 14-Pin Plastic DIP (P) 14-Pin SOIC (S) 14-Pin TSSOP (RU)
JA* JC
Model OP181GP OP181GS OP281GP OP281GS OP281GRU OP481GP OP481GS OP481GRU
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 8-Pin Plastic DIP 8-Pin SOIC 8-Pin Plastic DIP 8-Pin SOIC 8-Pin TSSOP 14-Pin Plastic DIP 14-Pin SOIC 14-Pin TSSOP
Package Option N-8 SO-8 N-8 SO-8 RU-8 N-14 SO-14 RU-14
Units C/W C/W C/W C/W C/W C/W
103 158 240 76 120 240
43 43 43 33 36 43
*JA is specified for the worst case conditions, i.e., JA is specified for device in socket for P-DIP packages; JA is specified for device soldered in circuit board for TSSOP and SOIC packages.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the OP181/OP281/OP481 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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OP181/OP281/OP481-Typical Characteristics
45 40
QUANTITY - Amplifiers
50 VS = +2.7V TA = +25 C 45 40 VS = +5V TA = +25 C
2000 1800 INPUT OFFSET VOLTAGE - V VS = +5V 1600 1400 1200 1000 800 600 400 200
QUANTITY - Amplifiers
35 30 25 20 15 10 5 0
-1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0
35 30 25 20 15 10 5 0
-1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0
0 -40 -20
0
INPUT OFFSET VOLTAGE - mV
INPUT OFFSET VOLTAGE - mV
20 40 60 80 100 120 TEMPERATURE - C
Figure 1. Input Offset Voltage Distribution
0 -0.5 VS = +5V
Figure 2. Input Offset Voltage Distribution
1.0 0.5 VS = +5V TA = +25 C
Figure 3. Input Offset Voltage vs. Temperature
0.5 0.4 VS = +5V 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -40 -20 0 20 40 60 80 100 120 TEMPERATURE - C
INPUT BIAS CURRENT - nA
-1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 -40 -20 0 20 40 60 80 100 120 TEMPERATURE - C
0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 COMMON-MODE VOLTAGE - Volts
Figure 4. Input Bias Current vs. Temperature
10,000 VS = +3V TA = +25 C 1,000
OUTPUT VOLTAGE - mV
Figure 5. Input Bias Current vs. Common-Mode Voltage
1,000 VS = +5V TA = +25 C
INPUT OFFSET CURRENT - nA
INPUT BIAS CURRENT - nA
Figure 6. Input Offset Current vs. Temperature
1,000 VS = 5V TA = +25 C
100 SOURCE 10 SINK
OUTPUT VOLTAGE - mV
100
OUTPUT VOLTAGE - mV
100
SOURCE 10 SINK
SOURCE 10 SINK
1.0
1.0
1.0
0.1
1
10 100 LOAD CURRENT - A
1000
0.1
1
10 100 LOAD CURRENT - A
1000
0.1
1
10 100 LOAD CURRENT - A
1000
Figure 7. Output Voltage to Supply Rail vs. Load Current
Figure 8. Output Voltage to Supply Rail vs. Load Current
Figure 9. Output Voltage to Supply Rail vs. Load Current
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OP181/OP281/OP481
70 60 50
OPEN-LOOP GAIN - dB
70 VS = +5V TA = +25 C RL = 100k 60 50 VS = +3V TA = +25 C RL = 100k
70 60 50 PHASE SHIFT - Degrees
0 45 90 135 180 225 270 1k 10k 100k FREQUENCY - Hz 1M
OPEN-LOOP GAIN - dB
VS = +2.7V TA = +25 C RL = 100k
PHASE SHIFT - Degrees
30 20 10 0 -10 -20 -30 100 1k 10k 100k FREQUENCY - Hz
PHASE SHIFT - Degrees
40
OPEN-LOOP GAIN - dB
0 45 90 135 180 225 270 1M
40 30 20 10 0 -10 -20 -30 100
40 30 20 10 0 -10 -20 -30 100 1k 10k 100k FREQUENCY - Hz
0 45 90 135 180 225 270 1M
Figure 10. Open-Loop Gain and Phase vs. Frequency
70 60 50
OPEN-LOOP GAIN - dB
Figure 11. Open-Loop Gain and Phase vs. Frequency
60 VS = +5V TA = +25 C RL = INFINITE
Figure 12. Open-Loop Gain and Phase vs. Frequency
PHASE SHIFT - Degrees
40 30 20 10 0 -10 -20 -30 100 1k 10k 100k FREQUENCY - Hz
0 45 90 135 180 225 270 1M
CLOSED-LOOP GAIN - dB
VS = 5V TA = +25 C RL = 100k TO GROUND
50 40 30 20 10 0 -10 -20 -30 -40 10 100
VS = +5V TA = +25 C MARKER @ 67nV/Hz
1k 10k 100k FREQUENCY - Hz
1M
50nV/Hz/Div
0
2k
4k 6k FREQUENCY - Hz
8k
10k
Figure 13. Open-Loop Gain and Phase vs. Frequency
90 80 70 60
CMRR - dB
Figure 14. Closed-Loop Gain vs. Frequency
160 140 VS = 5V, +5V, +3V, +2.7V TA = +25 C RL = INFINITE
Figure 15. Voltage Noise Density vs. Frequency
50
SMALL SIGNAL OVERSHOOT - %
VS = 5V VS = +5V
TA = +25 C
45 40 35 30 25 20 15 10 5
120 100
VS = +5V VIN = 50mV RL = 100k TA = +25 C
-OS +OS
PSRR - dB
50 40 30 20 10 0 -10 1k
VS = +3V
80 60 40 20 0 -20
10k
100k 1M FREQUENCY - Hz
10M
-40 10
100
1k 10k 100k FREQUENCY - Hz
1M
0 10
100 CAPACITANCE - pF
1000
Figure 16. CMRR vs. Frequency
Figure 17. PSRR vs. Frequency
Figure 18. Small Signal Overshoot vs. Load Capacitance
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OP181/OP281/OP481
5
MAXIMUM OUTPUT SWING - Vp-p
MAXIMUM OUTPUT SWING - Vp-p
3
4.0
SUPPLY CURRENT/AMPLIFIER - A
4 VS = +5V VIN = 4Vp-p RL = INFINITE TA = +25 C
VS = +3V VIN = 2Vp-p RL = INFINITE TA = +25 C 2
VS = +3V 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -40 -20
3
2
1
1
0 10
100
1k 10k FREQUENCY - Hz
100k
0 10
100
1k 10k FREQUENCY - Hz
100k
0
20 40 60 80 100 120 TEMPERATURE - C
Figure 19. Maximum Output Swing vs. Frequency
4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -40 -20 0 20 40 60 80 100 120 TEMPERATURE - C VS = +5V
Figure 20. Maximum Output Swing vs. Frequency
3.50 3.25 3.00 2.75 2.50 2.25 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0.00 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE - Volts TA = +25 C
Figure 21. Supply Current/Amplifier vs. Temperature
SUPPLY CURRENT/AMPLIFIER - A
SUPPLY CURRENT/AMPLIFIER - A
A2
100 90
0mV
VS = 2.5V AV = 1 RL = 100k CL = 50pF TA = +25 C
10 0%
50mV
100s
Figure 22. Supply Current/Amplifier vs. Temperature
Figure 23. Supply Current/Amplifier vs. Supply Voltage
Figure 24. Small Signal Transient Response
A2
100 90
0mV
VS = 1.35V AV = 1 RL = 100k CL = 50pF TA = +25 C
A2
100 90
2.50V
VS = +5V AV = 1 RL = 100k CL = 50pF TA = +25 C
A2
100 90
0.50V
VS = +2.7V AV = 1 RL = 100k CL = 50pF TA = +25 C
10 0%
10 0%
10 0%
50mV
100s
1V
100s
500mV
100s
Figure 25. Small Signal Transient Response
Figure 26. Large Signal Transient Response
Figure 27. Large Signal Transient Response
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OP181/OP281/OP481
120 105 VS = +5V TA = +25 C RL =
VS = 1.35V RL = VIN = 1Vp-p AT 2kHz
CHANNEL SEPARATION - dB
A2
100 90
2.50V
VS = +5V TA = +25 C
90 75 60 45 30 15
A2
100 90
0.00V
10 0%
10
0 -15 -30 100 1k 10k 100k FREQUENCY - Hz 1M
0%
1V
1V
200s
500mV
500mV
50s
Figure 28. No Phase Reversal
Figure 29. Channel Separation vs. Frequency
Figure 30. Saturation Recovery Time
A2
100 90
0.00V
VS = 2.5V CIRCUIT = AVOL
RL = TA = +25 C
10 0%
1V
500mV
100s
Figure 31. Saturation Recovery Time
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OP181/OP281/OP481
APPLICATIONS
THEORY OF OPERATION
where: VEE is the negative power supply for the amplifier, and VIN, MIN is the lowest input voltage excursion expected For example, an OP181 is to be used with a single supply voltage of 5 V where the input signal could possibly go as low as -1.0 V. Because the amplifier is powered from a single supply, VEE is ground, so the necessary series resistance should be 2 k.
Input Offset Voltage Nulling
The OPx81 family of op amps is comprised of extremely low powered, rail-to-rail output amplifiers, requiring less than 4 A of quiescent current per amplifier. Many other competitors' devices may be advertised as low supply current amplifiers but draw significantly more current as the outputs of these devices are driven to a supply rail. The OPx81's supply current remains under 4 A even with the output driven to either supply rail. Supply currents should meet the specification as long as the inputs and outputs remain within the range of the power supplies. Figure 32 shows a simplified schematic of the OP181. A bipolar differential pair is used in the input stage. PNP transistors are used to allow the input stage to remain linear with the commonmode range extending to ground. This is an important consideration for single supply applications. The bipolar front end also contributes less noise than a MOS front end with only nanoamps of bias currents. The output of the op amp consists of a pair of CMOS transistors in a common source configuration. This setup allows the output of the amplifier to swing to within millivolts of either supply rail. The headroom required by the output stage is limited by the amount of current being driven into the load. The lower the output current, the closer the output can go to either supply rail. Figures 7, 8 and 9 show the output voltage headroom versus load current. This behavior is typical of rail-to-rail output amplifiers.
VCC
The OPx81 family of op amps was designed for low offset voltages less than 1 mV. The single OP181 does provide two offset adjust terminals, should the user require greater precision. In general, these terminals should be used only to zero amplifier offsets and should not be used to adjust system offset voltages. A 20 k potentiometer connected to the offset adjust terminals, with the wiper connected to VEE, can be used to reduce the offset voltage of the amplifier. The OP181 should be connected in the unity-gain configuration (as shown in Figure 33) or in a gain configuration. The potentiometer should be adjusted until VOUT is minimized. The wiper of the potentiometer must be connected to VEE; connecting it to the positive supply rail could damage the device.
+5V
2
7
OP181
4 3 1 20k POT. 5
6
VOUT
VEE = -5V
OUT +IN -IN
Figure 33. Offset Voltage Nulling Circuit
Input Common-Mode Voltage Range
VEE
Figure 32. Simplified Schematic of the OP181
Input Overvoltage Protection
The input stage to the OPx81 family of op amps consists of a PNP differential pair. If the base voltage of either of these input transistors drops to more than 0.6 V below the negative supply, the input ESD protection diodes will become forward biased, and large currents will begin to flow. In addition to possibly damaging the device, this will create a phase reversal effect at the output. To prevent these effects from happening, the input current should be limited to less than 0.5 mA. This can be done quite easily by placing a resistor in series with the input to the device. The size of the resistor should be proportional to the lowest possible input signal excursion and can be found using the following formula:
R= VEE - VIN , MIN 0.5 x 10 -3
The OPx81 is rated with an input common-mode voltage range from VEE to 1 volt under VCC. However, the op amp can still operate even with a common-mode voltage that is slightly less than VEE. Figure 34 shows an OP181 configured as a difference amplifier with a single supply voltage of +3 V. Negative dc voltages are applied at both input terminals creating a commonmode voltage that is less than ground. A 400 mV p-p input signal is then applied to the noninverting input. Figure 35 shows a picture of the input and output waves. Notice how the output of the amplifier also drops slightly negative without distortion.
100k +3V 100k 100k -0.27V VIN = 1kHz AT 400mV p-p -0.1V 100k VOUT
OP181
Figure 34. OP181 Configured as a Difference Amplifier Operating at VCM < 0 V
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OP181/OP281/OP481
0.2ms
100
100 90
VOUT
90
0V VIN
10 0%
10 0%
0.1V
Figure 35. Input and Output Signals with VCM < 0 V
Overdrive Recovery Time
Figure 37. Ringing and Overshoot of the Output of the Amplifier
A Micropower Reference Voltage Generator
The amount of time it takes for an amplifier to recover from saturation can be an important consideration when using an amplifier as a comparator or when outputs can be driven to the supplies. The overdrive recovery time for the OP181 is 50 s with the amplifier running from a 3 volt supply and increases to 100 s with a 10 volt supply. Figure 36 shows the result of the OP181 running from a 3 V supply with its output being overdriven.
0.2ms
VIN SCALE 0.1V 0V
100 90
Many single supply circuits are configured with the circuit biased to 1/2 of the supply voltage. In these cases, a falseground reference can be created by using a voltage divider buffered by an amplifier. Figure 38 shows the schematic for such a circuit. The two 1 M resistors generate the reference voltage while drawing only 1.5 A of current from a 3 V supply. A capacitor connected from the inverting terminal to the output of the op amp provides compensation to allow for a bypass capacitor to be connected at the reference output. This bypass capacitor helps establish an ac ground for the reference output. The entire reference generator draws less than 5 A from a 3 V supply source.
+3V TO +12V
VS = +3V AV = +100
VOUT SCALE 1V
10 0%
0V
0.1V
10k 0.022F
Figure 36. Output of the Op Amp Recovering from Saturation
Capacitive Loading
2 1M 3 1M 1F 7
Most low supply current amplifiers have difficulty driving capacitive loads due to the higher currents required from the output stage for such loads. Higher capacitance at the output will increase the amount of overshoot and ringing in the amplifier's step response and could even affect the stability of the device. However, through careful design of the output stage and its high phase margin, the OPx81 family can tolerate some degree of capacitive loading. Figure 37 shows the step response of an OP181 with a 10 nF capacitor connected at the output. Notice that the overshoot of the output does not exceed more than 10% with such a load, even with a supply voltage of only +3 V.
OP181
4
100 6 1F VREF +1.5V TO +6V
Figure 38. A Micropower Bias Voltage Generator
A Window Comparator
The extremely low power supply current demands of the OPx81 family make it ideal for use in long life battery powered applications such as a monitoring system. Figure 39 shows a circuit that uses the OP281 as a window comparator.
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OP181/OP281/OP481
+3V +3V R1 VH A1 D1 +3V 5.1k 10k Q1 VOUT
R2 VIN 2k +3V
OP281-A
5.1k
creates a very small voltage drop. The voltage at the inverting terminal becomes equal to the voltage at the noninverting terminal through the feedback of Q1, which is a 2N2222 or equivalent NPN transistor. This makes the voltage drop across R1 equal to the voltage drop across RSENSE. Therefore, the current through Q1 becomes directly proportional to the current through RSENSE, and the output voltage is given by:
R2 VOUT = VEE - x RSENSE x I L R1
+3V D2 VL A2
R3
OP281-B
R4
The voltage drop across R2 increases with IL increasing, so VOUT decreases with higher supply current being sensed. For the element values shown, the VOUT transfer characteristic is -2.5 V/A, decreasing from VEE.
+5V R2 2.49k VOUT Q1 +5V
Figure 39. Using the OP281 as a Window Comparator
The threshold limits for the window are set by VH and VL, provided that VH > VL. The output of A1 will stay at the negative rail, in this case ground, as long as the input voltage is less than VH. Similarly, the output of A2 will stay at ground as long the input voltage is higher than VL. As long as VIN remains between VL and VH, the outputs of both op amps will be 0 V. With no current flowing in either D1 or D2, the base of Q1 will stay at ground, putting the transistor in cutoff and forcing VOUT to the positive supply rail. If the input voltage rises above VH, the output of A2 stays at ground, but the output of A1 will go to the positive rail, and D1 will conduct current. This creates a base voltage that will turn on Q1 and drive VOUT low. The same condition occurs if VIN falls below VL with A2's output going high, and D2 conducting current. Therefore, VOUT will be high if the input voltage is between VL and VH, and VOUT will be low if the input voltage moves outside of that range. The R1 and R2 voltage divider sets the upper window voltage, and the R3 and R4 voltage divider sets the lower voltage for the window. For the window comparator to function properly, VH must be a greater voltage than VL.
VH = VL = R2 R1 + R2 R4 R3 + R4
R1 100 0.1 RSENSE
OP181
RETURN TO GROUND
Figure 40. A Low-Side Load Current Monitor
Low Voltage Half-Wave and Full-Wave Rectifiers
Because of its quick overdrive recovery time, an OP281 can be configured as a full-wave rectifier for low frequency (<500 Hz) applications. Figure 41 shows the schematic.
R1 = 100k R2 = 100k +3V +3V 2k A2 VIN = 2V p-p A1 FULL-WAVE RECTIFIED OUTPUT
OP281-A
OP281-B
HALF-WAVE RECTIFIED OUTPUT
The 2 k resistor connects the input voltage to the input terminals to the op amps. This protects the OP281 from possible excess current flowing into the input stages of the devices. D1 and D2 are small-signal switching diodes (1N4446 or equivalent), and Q1 is a 2N2222 or equivalent NPN transistor.
A Low-Side Current Monitor
Figure 41. Single Supply Full- and Half-Wave Rectifiers Using an OP281
In the design of power supply control circuits, a great deal of design effort is focused on ensuring a pass transistor's long-term reliability over a wide range of load current conditions. As a result, monitoring and limiting device power dissipation is of prime importance in these designs. Figure 40 shows an example of a +5 V, single-supply current monitor that can be incorporated into the design of a voltage regulator with fold-back current limiting or a high current power supply with crowbar protection. The design capitalizes on the OP181's commonmode range that extends to ground. Current is monitored in the power supply return path where a 0.1 shunt resistor, RSENSE,
100 90
SCALE 0.1V/DIV
10 0%
SCALE 0.1ms/DIV
Figure 42. Full-Wave Rectified Signal
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REV. 0
OP181/OP281/OP481
Amplifier A1 is used as a voltage follower that will only track the input voltage when it is greater than 0 V. This provides a halfwave rectification of the input signal to the noninverting terminal of amplifier A2. When A1's output is following the input, the inverting terminal of A2 will also follow the input from the virtual ground between the inverting and noninverting terminals of A2. With no potential difference across R1, no current flows through either R1 or R2, therefore the output of A2 will also follow the input. Now, when the input voltage goes below 0 V, the noninverting terminal of A2 becomes 0 V. This makes A2 work as an inverting amplifier with a gain of 1 and provides a full-wave rectified version of the input signal. A 2 k resistor in series with A1's noninverting input protects the device when the input signal becomes less than ground.
A Battery Powered Telephone Headset Amplifier
Figure 43 shows how the OP281 can be used as a two-way amplifier in a telephone headset. One side of the OP281 can be used as an amplifier for the microphone, while the other side can be used to drive the speaker. A typical telephone headset uses a 600 speaker and an electret microphone that requires a supply voltage and a biasing resistor.
0.1F +3V 2.2k 11k +3V 1M 300k +3V 1F MIC OUT
The OP281-B amplifier can provide up to 15 dB of gain for the headset speaker. Incoming audio signals are ac coupled to a 10 k potentiometer that is used to adjust the volume. Again, two 1 M resistors provide the dc offset with a 1 F capacitor establishing an ac ground for the volume control potentiometer. Because the OP281 is a rail-to-rail output amplifier, it would have difficulty driving a 600 speaker directly. Here, a class AB buffer is used to isolate the load from the amplifier and also provide the necessary current drive to the speaker. By placing the buffer in the feedback loop of the op amp, crossover distortion can be minimized. Q1 and Q2 should have minimum betas of 100. The 600 speaker is ac coupled to the emitters to prevent any quiescent current from flowing in the speaker. The 1 F coupling capacitor makes an equivalent high pass filter cutoff at 265 Hz with a 600 load attached. Again, this does not pose a problem, as it is outside the frequency range for telephone audio signals. The circuit in Figure 43 draws around 250 A of current. The class AB buffer has a quiescent current of 140 A while roughly 100 A is drawn by the microphone itself. A CR2032 3 V lithium battery has a life expectancy of 160 mA hours, which means this circuit could run continuously for 640 hours on a single battery.
SPICE Macro-Model * OP181 SPICE Macro-model * 9/96, Ver. 1 * * Copyright 1996 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of this * model indicates your acceptance of the terms and provisions in * the License Statement. * * Node Assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT OP181 1 2 99 50 45 * * INPUT STAGE * Q1 4 13 PIX Q2 6 75 PIX I1 99 8 1.28E-6 EOS 7 2 POLY(1) (12, 98) 80E-6 1 IOS 1 2 1E-10 RC1 4 50 500E3 RC2 6 50 500E3 RE1 3 8 108 RE2 5 8 108 V1 99 13 DC .9 V2 99 14 DC .9 D1 3 13 DX D2 5 14 DX * * CMRR 76dB, ZERO AT 1kHz *
1F
OP281-A
ELECTRET 1M MIC
1F 10k
50k +3V
20k +3V INPUT 1F Q1 1F 10k POT. 1M 1F 1M
+3V
OP281-B
Q2 20k 600 SPEAKER
Figure 43. A Battery Powered Telephone Headset Two-Way Amplifier
The OP281-A op amp provides about 29 dB of gain for audio signals coming from the microphone. The gain is set by the 300 k and 11 k resistors. The gain bandwidth product of the amplifier is 95 kHz, which, for the set gain of 28, yields a -3 dB rolloff at 3.4 kHz. This is acceptable since telephone audio is band limited for 300 kHz to 3 kHz signals. If higher gain is required for the microphone, an additional gain stage should be used, as adding any more gain to the OP281 would limit the audio bandwidth. A 2.2 k resistor is used to bias the electret microphone. This resistor value may vary depending on the specifications on the microphone being used. The output of the microphone is ac coupled to the noninverting terminal of the op amp. Two 1 M resistors are used to provide the dc offset for single supply use. REV. 0
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OP181/OP281/OP481
ECM1 11 98 POLY(2) (1, 98) (2, 98) 0 .5 .5 R1 11 12 1.59E6 C1 11 12 100E-12 R2 12 98 283 * * POLE AT 900kHz * EREF 98 0 (90, 0) 1 G1 98 20 (4, 6) 1E-6 R3 20 98 1E6 C2 20 98 177E-15 * * POLE AT 500kHz * E2 21 98 (20, 98) 1 R4 21 22 1E6 C3 22 98 320E-15 * * GAIN STAGE * CF 45 40 8. 5E-12 R5 40 98 65. 65E6 G3 98 40 (22, 98) 4.08E-7 D3 40 41 DX D4 42 40 DX V3 99 41 DC 0.5 V4 42 50 DC 0.5 * * OUTPUT STAGE * ISY 99 50 1.375E-6 RS1 99 90 10E6 RS2 90 50 10E6 M1 45 46 99 99 POX L=1.5u W=300u M2 45 47 50 50 NOX L=1.5u W=300u EG1 99 46 POLY(1) (98, 40) 0.77 1 EG2 47 50 POLY(1) (40, 98) 0.77 1 * * MODELS * .MODEL POX PMOS (LEVEL=2, KP=25E-6, VTO=-0.75, LAMBDA=0.01) .MODEL NOX NMOS (LEVEL=2, KP=25E-6, VTO=0.75, LAMBDA=0.01) .MODEL PIX PNP (BF=200) .MODEL DX D(IS=1E-14) .ENDS
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OP181/OP281/OP481
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP (N-8)
0.430 (10.92) 0.348 (8.84)
8 5
14-Lead Plastic DIP (N-14)
0.795 (20.19) 0.725 (18.42)
14 8 7
0.280 (7.11) 0.240 (6.10)
1 4
1
0.280 (7.11) 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN
PIN 1 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93)
0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN SEATING PLANE
0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)
PIN 1 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356)
0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)
0.022 (0.558) 0.100 0.070 (1.77) 0.014 (0.356) (2.54) 0.045 (1.15) BSC
0.015 (0.381) 0.008 (0.204)
0.100 0.070 (1.77) (2.54) 0.045 (1.15) BSC
SEATING PLANE
0.015 (0.381) 0.008 (0.204)
8-Lead SOIC (SO-8)
0.1968 (5.00) 0.1890 (4.80)
8 1 5 4
14-Lead Narrow Body SOIC (SO-14)
0.3444 (8.75) 0.3367 (8.55)
14 1 8 7
0.1574 (4.00) 0.1497 (3.80)
0.2440 (6.20) 0.2284 (5.80)
0.1574 (4.00) 0.1497 (3.80)
0.2440 (6.20) 0.2284 (5.80)
PIN 1 0.0098 (0.25) 0.0040 (0.10)
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) x 45 0.0099 (0.25)
PIN 1 0.0098 (0.25) 0.0040 (0.10)
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) x 45 0.0099 (0.25)
SEATING PLANE
0.0500 0.0192 (0.49) (1.27) 0.0138 (0.35) BSC
0.0098 (0.25) 0.0075 (0.19)
8 0
0.0500 (1.27) 0.0160 (0.41)
SEATING PLANE
0.0500 (1.27) BSC
0.0192 (0.49) 0.0138 (0.35)
0.0099 (0.25) 0.0075 (0.19)
8 0
0.0500 (1.27) 0.0160 (0.41)
8-Lead TSSOP (RU-8)
0.122 (3.10) 0.114 (2.90)
14
14-Lead TSSOP (RU-14)
0.201 (5.10) 0.193 (4.90)
8
0.177 (4.50) 0.169 (4.30)
0.177 (4.50) 0.169 (4.30)
0.256 (6.50) 0.246 (6.25)
1
1
4
7
PIN 1 0.006 (0.15) 0.002 (0.05) 0.0256 (0.65) BSC 0.0433 (1.10) MAX 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) 0.006 (0.15) 0.002 (0.05) 0.028 (0.70) 0.020 (0.50)
PIN 1 0.0433 (1.10) MAX 0.0256 (0.65) BSC 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090)
0.256 (6.50) 0.246 (6.25)
8
5
SEATING PLANE
8 0
SEATING PLANE
8 0
0.028 (0.70) 0.020 (0.50)
REV. 0
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C2195-12-10/96
PRINTED IN U.S.A.

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